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Internship: An energy proportional neuromorphic solution for SpikeNets

Research Internship Project
An energy proportional neuromorphic solution for SpikeNets.

Context
Spiking neural networks are considered as the third generation of neural networks and could thus
replace the conventional networks used in machine learning in order to reduce energy consumption
of AI, especially in Edge applications.
But taking advantage of SNN needs to efficiently parallelize their execution onto multiple
neuromorphic (event-based) processors (NPU) according to the effective profile of activity in terms
of spikes generated in each layer of the network.
The literature didn’t addressed the question of energy proportional execution of SNN on parallel
architectures such as Loihi 2 [3], Spinnaker[2] or SPLEAT [1].
The goal of this position is to develop such a solution.


Project mission
The project mission will be organized in several periods:

  • Review of neuromorphic hardware architectures
  • Introduction to training of spiking neural networks
  • Introduction to the execution of SNN on SPLEAT
  • Profiling of activity of SNN over different datasets
  • Profiling of energy consumption of SPLEAT on FPGA and comparison between parallel and
    sequential versions of the architecture
  • Integration of SPLEAT into a RISC-V based SoC (GRlib)
  • Development of an estimation method of energy consumption of SNN
  • Study of the impact of activity and latency on energy consumption
  • Writing of a publication in international conference

References
[1] Abderrahmane, Miramond et al. SPLEAT: SPiking Low-power Event-based ArchiTecture for in-orbit processing of satellite imagery, IJCNN 2022.
[2] SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning, Christian Mayr, Sebastian Hoeppner, Steve Furber, Arxiv:1911.02385, 2019
[3] Efficient Neuromorphic Signal Processing with Loihi 2, Garrick Orchard, E. Paxon Frady, Daniel Ben Dayan Rubin, Sophia Sanborn, Sumit Bam Shrestha, Friedrich T. Sommer, Mike Davies, arXiv:2111.03746, 2021


Practical information
Location: LEAT Lab / SophiaTech Campus, Sophia Antipolis, LIRMM, Montpellier
Duration: 6 months from March 2025
Profile: electronic engineer, VHDL programming, FPGA, embedded programming, machine learning
Research keywords: FPGA, Embedded systems, Edge AI, Spiking neural networks


Contact and supervision
Benoît Miramond
LEAT Lab – University Cote d’Azur / CNRS
Polytech Nice Sophia
04.89.15.44.39. / firstname.name@univ-cotedazur.fr
Gilles Sassatelli
Lirmm, Montpellier

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